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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
Table 17. Reg 0Ah CP Op Amp Register
Bit
name
Width
Default
Description
[1:0]
cp_opamp_bias_sel
2
0
charge Pump internal op-amp bias select
00 - 540 a
01 - 689 a
10 - 943 a
11 - 1503 a
Enabled with chg Pump enable
note: this circuit affects internal charge pump operation and linearity. Default
setting is recommended. Enabled with reg08h[1] cp_en
Table 18. Reg 0Bh PFD Register
Bit
name
Width
Default
Description
[2:0]
pfd_del_sel
3
0
sets PFD reset path delay. recommended value 010
When in integer mode, reg B Bits [2:0] should not be 000 because it doesn’t
ensure sufficient ‘on’ time for the cP at 50MHz. this isn’t an issue in Fractional
Mode;
[3]
pfd_phase_sel
1
0
Swaps the PFD inputs
1 negative Vco tuning slope
0 positive Vco tuning slope
[4]
pfd_up_en
1
enables the PFD UP output according to state of
pfd_mute_when_locked_enable, see Reg0B<9>
[5]
pfd_dn_en
1
enables the PFD Dn output according to state of
pfd_mute_when_locked_enable, see Reg0B<9>
[6]
pfd_LD_opEn
1
pfd Lock Detect output Enable, enables Lock Detect flag output to LD_SDo pin
[7]
pfd_pullup_ctrl
1
0
Forces PFD UP output on
[8]
pfd_puldn_ctrl
1
0
Forces PFD Dn output on
[9]
pfd_mute_when_locked_
enable
1
0
1: if set:
when locked disables UP if pfd_up_en=0
when locked disables Dn if pfd_dn_en=0
when not locked, allows both UP and Dn to be active and ignores pdf_up_en
and pfd_dn_en
0: if clear, pfd_dn_en and pfd_up_en enable UP and Dn
outputs at all times
[10]
spare0
1
0
reserved
[11]
spare1
1
reserved
Table 19. Reg 0Ch VCO SPI Register
Bit
name
Width
Default
Description
[9:0]
vcospi_vco_data
10
0
data register contents, when written automatically outputs
this data via Vco SPi when to_gpo_sdo=1 Reg09<7>
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